1. Field of the Invention
The present invention relates to package structures, and more particularly, to a heat-conductive package structure.
2. Description of Related Art
Owing to advances in semiconductor package technology, there are various packages for semiconductor devices nowadays. Ball Grid Array (BGA) is an advanced semiconductor package technique, characterized by mounting a semiconductor chip on a package substrate, and having a plurality of solder balls arranged in a grid array and formed on the back of the package substrate, thereby increasing the number of I/O connections in unit area. Ball Grid Array not only meets the high integration requirements for a semiconductor chip but also enables the semiconductor chip to be electrically connected to an external device via solder balls.
With the electronic industry booming, electronic products are becoming more multi-function and high-performance. To meet the packaging requirements for high integration and miniaturization of semiconductor packages, semiconductor chips nowadays generate an increasingly great amount of heat during operation. Failure to timely dissipate the heat generated by semiconductor chips can deteriorate the performance of the semiconductor chips and shorten the life of the semiconductor chips.
FIG. 1 is a cross-sectional view showing a semiconductor component mounted on a conventional circuit board. The carrier board 100 has a first surface 100a and a second surface 100b. The carrier board 100 is a circuit board with a circuit. The first surface 100a and the second surface 100b are formed with a first dielectric layer 11a and a second dielectric layer 11b thereon respectively. The first and second dielectric layers 11a, 11b are formed with first and second circuit layers 12a, 12b thereon respectively. The first circuit layer 12a has first electrically connecting pads 121a and second electrically connecting pads 122a thereon. The second circuit layer 12b has third electrically connecting pads 121b thereon. At least a plated through hole (PTH) 13 is formed in the carrier board 100 and the first and second dielectric layers 11a, 11b to electrically connect the first and second circuit layers 12a, 12b. An insulating protective layer 14 is formed on the first and second dielectric layers 11a, 11b and first and second circuit layers 12a, 12b. Insulating protective layer openings 140, 141 are formed in the insulating protective layer 14 to expose the first and second electrically connecting pads 121a, 122a and third electrically connecting pads 121b. A metal protective layer 16 made of nickel/gold (by nickel-plating and then gold-plating) is formed on the surfaces of the first, second and third electrically connecting pads 121a, 122a and 121b. A conductive element 15, such as a solder ball, is formed on the metal protective layer 16 on the first and third electrically connecting pads 121a, 121b for electrical connection with another electronic device. A semiconductor component 17 is mounted on the insulating protective layer 14 on the first surface 100a of the carrier board 100. The semiconductor component 17 has an active surface 17a and an inactive surface 17b opposing to the active surface 17a. A plurality of electrode pads 171 are formed on the active surface 17a of the semiconductor component 17. The semiconductor component 17 is mounted on the first surface 100a of the carrier board 100 via the inactive surface 17b. The second electrically connecting pads 122a covered with the metal protective layer 16 are exposed from the insulating protective layer opening 141 of the insulating protective layer 14. A second conductive element 18, such as a metal wire, is formed on the metal protective layer 16 to electrically connect the electrode pads 171 on the semiconductor component 17 and the second electrically connecting pads 122a. Afterward, an encapsulant 19 encapsulates and thereby protects the wire-bonded second conductive element 18 and semiconductor component 17.
Nevertheless, heat generated by the packaged semiconductor component 17 on the first dielectric layer 11a is unlikely to be dissipated efficiently. Also, the inactive surface 17b of the semiconductor component 17 is in contact with the insulating protective layer 14, but the insulating protective layer 14 is almost incapable of heat dissipation. As a result, the semiconductor component 17 is likely to be overheated and damaged.
FIG. 2A is a cross-sectional view showing a semiconductor component mounted on another conventional circuit board, in which a carrier board 100 (like the one shown in FIG. 1) with a first surface 100a is provided. An opening 110a is formed in a first dielectric layer 11a disposed on the first surface 100a to expose the carrier board 100. An insulating protective layer opening 142 is formed in the insulating protective layer 14 disposed on the first dielectric layer 11a to expose the second electrically connecting pads 122a on the first circuit layer 12a formed on the first dielectric layer 11a and the opening 110a of the first dielectric layer 11a. The metal protective layer 16 is formed on the second electrically connecting pads 122a. The inactive surface 17b of the semiconductor component 17 is in contact with a portion of the carrier board 100 exposed from the opening 110a. The second conductive element 18 electrically connects the electrode pads 171 on the active surface 17a of the semiconductor component 17 and the metal protective layer 16 on the second electrically connecting pads 122a. The encapsulant 19 encapsulates and thereby protects the wire-bonded second conductive element 18 and semiconductor component 17. The semiconductor component 17 is received in the opening 110a, so as to reduce the total thickness of the semiconductor package.
The semiconductor component 17 is embedded in the opening 110a of the first dielectric layer 11a to shorten an electrical conduction path, lessen signal loss and distortion, enhance high-speed performance, and downsize a wire-bonded and encapsulated semiconductor package. But little heat conduction or heat dissipation takes place through the contact between the carrier board 100 and the inactive surface 17b of the semiconductor component 17. As a result, heat generated by the semiconductor component 17 in operation cannot be efficiently dissipated.
FIG. 2B is a cross-sectional view showing semiconductor components stacked up and mounted on another conventional circuit board. The semiconductor component 17 includes a first semiconductor chip 17′ and a second semiconductor chip 17″ stacked on the first semiconductor chip 17′. The first semiconductor chip 17′ is mounted on a portion of the carrier board 100 exposed from the opening 110a, via the inactive surface 17b of the first semiconductor chip 17′. The electrode pads 171′, 171″ on the first semiconductor chip 17′ and the second semiconductor chip 17″ are electrically connected to the metal protective layer 16 on the second electrically connecting pads 122a, via the second conductive element 18.
The second semiconductor chip 17″ is stacked on the first semiconductor chip 17′, wherein the inactive surface 17b″ of the second semiconductor chip 17″ in connected to the active surface 17a′ of the first semiconductor chip 17′. The first semiconductor chip 17′ is mounted on the carrier board 100 via the inactive surface 17b′, but the carrier board 100 is unfit for heat conductive and heat dissipation. Hence, heat generated by the semiconductor component in operation cannot be efficiently dissipated.
It is an urgent issue to develop a heat-conductive package structure in order to enhance heat dissipation of a semiconductor component in operation, downsize a semiconductor package, and overcome the drawbacks of the prior art.